1. Technical Field
A method of forming copper wiring in a semiconductor device is disclosed. More particularly, a method of forming copper wiring in a semiconductor device capable of preventing a dishing phenomenon or an erosion phenomenon occurring on the surface of the copper wiring when the copper wiring is formed in damascene patterns by polishing the copper layer using a chemical mechanical polishing (CMP) process.
2. Description of the Related Art
In general, as the semiconductor industry shifts to ultra large-scale integration (ULSI), the geometry of semiconductor devices is narrowed to a sub-half-micron scale. The circuit density is increased improve performance and reliability. Thin copper films can improve reliability of the semiconductor device since they have a higher melting point than aluminum and thus have a higher resistance to electromigration (EM). Further, thin copper films can increase the signal transfer rate due to their low resistivity. Accordingly, when forming metal wirings in semiconductor devices, thin copper films have been used as an interconnection material useful for integration circuits.
Today, available methods of burying copper include a physical vapor deposition (PVD) method, a reflow method, a chemical vapor deposition method (CVD) method, an electroplating method, an electroless-plating method, and the like. Of them, the electroplating method and the CVD method, which have good copper burial characteristics, have been preferably used.
A damascene scheme has been widely used by which a via contact hole to which a lower layer will be electrically connected and a trench where a metal wiring will be located are simultaneously formed in the process of forming the copper wirings in the semiconductor device, while using copper as the material for the metal wiring. At this time, an insulating material of a low dielectric constant is used as an interlayer insulating film on which the damascene patterns will be formed.
In order to form copper wirings in damascene patterns having a via contact hole and a trench, copper is buried within the damascene patterns by the above method. The buried copper layer is then polished by means of the CVD process, thereby isolating it from a neighboring copper wiring.
Referring now to FIG. 1, a method of forming the copper wirings in the semiconductor device using the electroplating method according to a first embodiment of the prior art will be described.
An interlayer insulating film 11 is formed on a substrate 10. A plurality of damascene patterns 12 having different densities from the interlayer insulating film 11 are then formed by means of a damascene scheme.
Next, a copper barrier metal layer 13 and a copper seed layer 14 are sequentially formed along the surface of the interlayer insulating film 11 including the plurality of the damascene patterns 12. At this time, the copper bearing metal layer 13 may be formed using one of ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN and CVD WN. Further, the copper seed layer 14 may be formed using various methods but is preferably formed using an ionized PVD method. A wafer on which the copper seed layer 14 is formed is loaded onto the electroplating apparatus in which a copper plating solution to which organic additives of two types called an accelerator and a suppressor are added is filled. With a negative (−) power supply applied to the wafer, copper is plated until the damascene patterns 12 are sufficiently filled, so that a copper layer 15 is formed.
Thereafter, the copper layer 15, the copper seed layer 14 and the copper barrier metal layer 13 are sequentially polished by means of chemical mechanical polishing process until the to surface of the interlayer insulating film 11 is exposed. Copper wirings are thus formed within the plurality of the damascene patterns 12.
In the above first embodiment, the organic additives of the two types called the accelerator and the suppressor are added to the copper plating solution in order to sufficiently fill the damascene patterns 12. During the electroplating process, a phenomenon occurring due to a reciprocal action of these additives, i.e., a “bumping phenomenon” or “sloping phenomenon” occurs at portions where the damascene patterns 12 are densely formed, as shown in FIG. 1. At this time, the thickness of the copper layer 15 at the portions where the bumping phenomenon occurs becomes unnecessarily thicker than other portions. IF the chemical mechanical polishing process is performed in this state, there is a problem that a “dishing” phenomenon or an “erosion” phenomenon may occur on the top surface of the copper wiring.
FIG. 2 is a cross-sectional view of a semiconductor device for explaining a method of forming the copper wirings in the device using the electroplating method according to a second embodiment of the prior art. The purpose of the second embodiment is to propose a solution for solving the problems encountered in the first embodiment.
It should be noted that the method of forming the copper wirings according to the second embodiment is similar to the first embodiment. Therefore, the same processes of the second embodiment to those of the first embodiment will not be explained but other portions different from the first embodiment will be explained.
In FIG. 2, a reference numeral ‘20’ indicates a substrate, a reference numeral ‘21’ indicates an interlayer insulating film, a reference numeral ‘22’ indicates a damascene pattern, a reference numeral ‘23’ indicates a copper barrier metal layer, a reference numeral ‘24’ indicates a copper seed layer, and a reference numeral ‘25’ indicates a copper layer.
In the second embodiment, unlike the first embodiment, a copper electroplating process is performed by adding a third additive called a leveler to the copper plating solution to which the organic additives of the two kinds called the accelerator and the suppressor are added. By adding the third additive called the leveler, the bumping or also sloping phenomenon occurring at the portions where the damascene patterns 22 are densely formed is less severe than in the first embodiment, as shown in FIG. 2. Though the bumping phenomenon in the second embodiment is less severe than in the first embodiment, the portions where the damascene patterns 22 are densely formed are unnecessarily thicker than those where the damascene patterns 22 are not densely formed. This presents a problem with respect to the subsequent chemical mechanical polishing process. Further, the amount of the additives increase due to addition of another organic additive. Accordingly, there is a problem that physical characteristics such as an electrical characteristic, etc. are degraded since a problem that the organic impurity may be introduced within the copper wirings is increased.